What is RF sampling?
RF Sampling is a technique to convert the RF signal to digital signal using an ADC directly, without an analog frequency conversion of intermediate frequency (i.e., low IF or Zero IF). By using this method RF sampling ADC can replace the conventional radio signal path subsystem of mixers, LO synthesizer, IF amplifiers and filters etc. like in a heterodyne architecture.
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| Super-heterodyne Architecture |
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| RF Sampling System |
Advantages of direct RF Sampling
The main advantages of direct RF sampling have fewer channels, a lower cost per channel, and a lower channel density.
Architectures that use direct RF sampling can make synchronization easier. For RF systems, it must synchronize the internal clocking of the RF instruments and the LOs in order to achieve phase coherence. You can focus entirely only on the clock synchronization of device when using direct sampling, which doesn't require LOs.
Challenges of RF Sampling
The key challenges associated with RF sampling are:
- Receiver Sensitivity
- In-Band Blocking
- Out-of-Band Blocking
Receiver Sensitivity
The lowest power level at which a receiver can detect an RF signal and demodulate data is known as receiver sensitivity. The noise figure of the receiver chain is one of the main factors which affects sensitivity. In a heterodyne architecture, the signal chain has enough gain before the ADC so that the ADC noise figure has little effect on the sensitivity.
Adding an amplifier before an ADC is the most popular method for reducing noise. So, in RF sampling system LNAs are required before the ADC to decrease the overall noise figure of the receiver chain.
In-Band Blocking
The receiver's ability to demodulate weaker signals in the presence of an in-band interferer is measured by the receiver's in-band blocking performance. Interfering signals can enter the front-end filter passband. Additionally, the in-band interference power level is high while the desired signal power level is low. As a result, the high interference power level may saturate the ADC, or the desired signal may be lost in noise due to the limited SFDR of the ADC. A perfect frequency plan can minimize the reduction in SFDR of ADC caused by low-order harmonics. Also, the phase noise of the sampling clock (jitter) mixes with the interfering signal. Therefore, a better phase noise performance clock is required.
Out-of-Band Blocking
Regardless of architecture, the ADC input needs to be shielded from strong out-of-band interference because it could alias the in-band signal, causing it to exceed the ADC full scale and saturate the receiver, or it could generate harmonics that would overlap with a weak, in-band desired signal. When frequency planning is used, the filter design for RF-sampling systems becomes a little bit more relaxed. Low-order harmonics, or interleaving spurs of out-of-band interferers, still need to be considered even though there are no mixer images or LO spurs to be concerned about.
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